DDR and PCIe PCB Design

Flux is an AI hardware engineer. It plans and routes high-speed PCB interfaces from their stackup and timing requirements.

Plan the stackup and impedance targets

Ask Flux to set up the board stackup and impedance rules before routing.

Set up the stackup and impedance targets for a DDR4 and PCIe board.

Use the interface requirements to choose layer roles and set each pair's impedance.

Plan a stackup with continuous ground references for the DDR and PCIe routes.

Set up the stackup for this LPDDR4 board and apply its impedance rules.

Set the layer roles, reference planes, materials, and target impedances before you route the interfaces. Flux applies the impedance rules from the stackup to the nets and pairs.

Use the Stackup Editor to review or edit the layer stackup. For impedance setup, see Impedance Control.

Route DDR data lanes to their strobes

Ask Flux to route each DDR byte lane and match its data signals to the strobe.

Route each DDR4 data byte lane and match its length to its strobe within 0.2 mm.

Route the LPDDR4 data lanes with the listed order and pitch. Report delay and skew to each strobe.

Set the DDR data targets from the stackup delay and keep the lane-to-strobe skew within budget.

Review the DDR lanes and report each lane's length, delay, and skew to its strobe.

Flux length-matches the byte lanes to their strobe. It uses the stackup propagation delay to calculate delay from trace length and can report the delay and skew for each lane in picoseconds.

For a route-length workflow, see Length and Skew Tuning. For timing-budget planning, see Plan DDR topology and timing budgets.

Choose a DDR address and command topology

Ask Flux to use the topology that fits the DDR interface.

Route the DDR4 address, command, and clock nets in a fly-by topology.

Plan a T-branch topology for the address and command signals.

Add VTT termination for the DDR address and command nets.

Compare fly-by and T-branch routing for this memory interface.

Flux can route address, command, and clock signals in a fly-by or T-branch topology. Include the termination and timing requirements in your request.

Fan out the memory and processor BGA

Ask Flux to escape the BGA pads with the via types defined in the stackup.

Fan out the memory BGA with the blind and buried vias from the stackup.

Escape the processor BGA using microvias between the top layers.

Route the DDR signals from the SoC and memory BGAs with neckdowns at fine-pitch pads.

Fan out the fine-pitch memory connections and keep the signal lanes in their groups.

Flux uses the configured via types and spans to fan out the processor and memory connections. It can use neckdowns where fine-pitch pads need narrower traces.

Set the available via types in the Stackup Editor. See HDI and BGA PCB Design for via spans and dense-part escape routing.

Route PCIe and other differential interfaces

Ask Flux to route differential pairs from the impedance targets in the stackup.

Route the PCIe lanes at 85 ohms from the stackup and keep each pair's skew below 0.1 mm.

Route USB 3 and HDMI pairs at their stackup impedances with the specified intra-pair skew.

Route Ethernet pairs at 100 ohms and keep each pair over its reference plane.

Route the PCIe TX and RX pairs and keep their impedance and skew within the target values.

PCIe, USB 3, HDMI, and Ethernet use impedance-controlled differential pairs. Common targets are 85, 90, or 100 ohms, as defined by the stackup. Set the maximum intra-pair skew with each pair.

For length targets and meander choices, see Length and Skew Tuning.

Place PCIe AC-coupling capacitors

Ask Flux to place AC-coupling capacitors on the PCIe transmit lanes near the transmitter.

Place the PCIe TX AC-coupling capacitors close to the transmitter.

Add the required AC-coupling capacitors to each PCIe transmit lane.

Place the PCIe coupling capacitors without changing the receiver-side routing.

Review the PCIe transmit lanes and position their AC-coupling capacitors near the source.

Flux places the capacitors on the PCIe TX lanes near the transmitter. Include the transmitter and lane names in your request when the board has more than one PCIe interface.

Keep a continuous reference and return path

Ask Flux to review each high-speed route's reference plane and layer transitions.

Keep the PCIe pairs over a continuous reference plane.

Add return vias where the DDR clock routes change layers.

Review every high-speed layer transition and add return vias at the transitions.

Check the reference path under the USB 3 and HDMI pairs.

Keep each pair over a continuous reference plane. Add return vias when a high-speed route changes layers.

Analyze routed signals

Ask Flux to simulate the routed high-speed signals and report the results.

Run an electromagnetic simulation of the PCIe lanes and report SDD11, SDD21, and differential impedance.

Check the DDR routes for crosstalk and TDR response.

Generate an eye diagram for the PCIe channel at 16 Gbps and report eye height and width.

Review the board for signal-integrity issues and fix the issues you find.

The analysis can report SDD11, SDD21, differential impedance, TDR, crosstalk, and eye diagrams at a bit rate up to 20 Gbps. It also analyzes routed via transitions as part of the board.

See Signal Integrity Simulation and Review for simulation and review steps. For electromagnetic design review, see EMC Design Review for PCBs.

Review EMC and manufacturing checks

Ask Flux to review the board for EMC and run the design checks.

Review this board for EMC issues around the PCIe and DDR interfaces.

Check the high-speed routes for reference-plane gaps and missing return vias.

Run the design checks and list the issues that affect the DDR interface.

Review the board before manufacturing and report the EMC findings.

Flux can review the board for EMC issues, including signal paths that cross reference-plane gaps and layer changes without return vias. See EMC Design Review for PCBs and EMC review.

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