Length and Skew Tuning

Flux is an AI hardware engineer. It routes and tunes PCB traces to meet length and timing targets.

Tune one net to a target length

Ask Flux to route a net to an absolute length. Give a tolerance in millimeters when you need a specific range.

Route CLK_OUT to 42 mm with a 0.2 mm tolerance.

Tune the trace from U1 pin 4 to J2 pin 3 to 68 mm.

Extend DATA_READY to 35 mm without changing the board outline.

Route the sensor clock to 51 mm and keep it on the top layer.

Flux routes the net to the target length. It uses a meander where the route needs added length.

Match lengths between nets

Ask Flux to match the pin-to-pin length of one net to another. This is useful when two routes must have similar electrical path lengths.

Match DATA1 to the pin-to-pin length of DATA0 within 0.15 mm.

Match the two encoder outputs within 0.25 mm.

Make the SPI clock and data paths the same length within 0.3 mm.

Match the sensor pair from the connector pins to the MCU pins within 0.2 mm.

Name the reference net and the allowed tolerance. Flux measures each route between its connected pins and tunes the route to match.

Set skew limits for pairs and groups

Ask Flux to set a maximum skew for a differential pair or a group of nets.

Route USB_P and USB_N as a differential pair with no more than 0.1 mm of skew.

Keep the LVDS pair skew below 0.08 mm.

Keep the clock-to-data skew in this bus below 0.2 mm.

Match each DDR data lane to its strobe and keep lane-to-strobe skew below 15 ps.

For pair constraints, set PN Skew Max in the terminal properties. For bus constraints, set Pair to Pair Skew Max. These properties use picoseconds. See Differential Pair Constraints and Bus Constraints.

Use a length tolerance in millimeters when you specify routed lengths. Use a skew limit in picoseconds when you specify the timing difference between signals.

Route length-matched buses

Ask Flux to route parallel lanes with the order, pitch, and shared path that the interface needs.

Route this QSPI bus in the listed lane order and match all lanes within 0.2 mm.

Route the SDIO data bus and clock in parallel with 0.25 mm lane pitch.

Route the display data bus as parallel lanes with this order and pitch, then report lane lengths.

Route the camera bus with a shared path and keep the data-to-clock skew below 20 ps.

Name each lane in order. Give the pitch, target length or reference net, and allowed mismatch. Flux routes the lanes together and reports each lane's length and skew.

You can use this approach for DDR data, parallel displays, camera buses, QSPI, and SDIO. You can also ask Flux to match clocks and other grouped signals.

Choose a meander style

Ask Flux to choose or change the meander style used to add route length.

Tune the selected net with trombone meanders.

Use accordion meanders to match these three traces.

Use a sawtooth meander on the clock route and keep the corners smooth.

Add length to the short lane with a trombone meander.

Trombone meanders are the default. You can request accordion or sawtooth meanders. Flux adds arcs when the available corner radius allows them.

Set a length target for a differential pair

Ask Flux to route a differential pair and tune its length as part of the same request.

Route the PCIe TX pair at its stackup impedance and tune both nets to 120 mm.

Route the HDMI clock pair and match its pin-to-pin length to the data pairs.

Route the Ethernet pair with a 0.1 mm intra-pair length mismatch.

Route the LVDS pair to 85 mm and keep the pair skew below 10 ps.

Set the pair's impedance and skew requirements in the stackup and pair properties. Flux keeps the pair together while it adjusts the route length. For the pair setup, see Impedance Control.

Convert length to delay for a timing budget

Ask Flux to use the stackup propagation delay to calculate trace delay and set route targets from a timing budget.

Calculate the delay for each DDR data lane from the board stackup.

Set the trace length targets for this interface from its 250 ps timing budget.

Report the propagation delay and lane-to-strobe skew in picoseconds.

Plan the DDR topology and timing budget from the trace lengths and stackup delay.

Trace delay depends on the stackup. Flux uses the propagation delay of the selected stackup to convert route length to time. It can set length targets from the timing budget and report delay per lane.

For DDR topology and timing-budget steps, see Plan DDR topology and timing budgets.

Tune lengths on flex and rigid-flex boards

Ask Flux to tune routes through flex areas using the stackup for each area.

Match the two flex-tail signals within 0.2 mm using the flex area's stackup.

Tune the rigid-to-flex clock path to its target delay.

Keep the traces matched across the two flex arms and report each lane's length.

Add a pad neckdown where the tuned flex trace meets the fine-pitch connector.

Flux uses the stackup of each Stackup Area to calculate impedance and electrical length. It can use neckdowns at pads while it routes and tunes a trace.

For area stackups and flex design checks, see Flex and Rigid-Flex Boards.

Check lengths and skew

Ask Flux to report the tuned lengths and skew after routing.

Report the pin-to-pin length of each net in this bus and its skew from the target.

List the length and delay of every DDR lane and its skew to the strobe.

Show the length mismatch for each differential pair on this board.

Review the routed signals for impedance, crosstalk, and length mismatch.

Flux reports the resulting lane lengths and skew. Ask Flux to review routed signals when you also need signal-integrity analysis. See Signal Integrity Simulation and Review.

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