Route with Flux

Flux is an AI hardware engineer. It routes your PCB, tunes pairs and lengths, and edits existing routes as part of the complete device you design.

Ask Flux to route the whole board or the nets and connections you name. You can also select traces, vias, or parts in the PCB editor and ask Flux about the selection.

Prepare the board for routing

Ask Flux to review the routing inputs before it routes the board.

Check the stackup, net widths, clearances, and layer assignments before routing.

Set up the board size, stackup, and width and clearance rules for this schematic before routing.

Route the board with the USB D+ and D- pair at 90 ohms. Keep the antenna area clear.

Open Chat and describe your routing requirements. Routing uses the schematic nets, board size, stackup, and width and clearance rules. Ask Flux to set these up as part of your request.

For stackup and impedance setup, see Impedance control and the Stackup Editor.

Route the whole board

Ask Flux to route the whole board. You can pause board routing and resume it later.

Route the whole board. Keep the existing copper and component placement.

Pause board routing.

Resume board routing.

Open Chat and send your board routing request. Send a pause or resume request in the conversation when you need it.

Route selected connections

Ask Flux to route only the nets or connections you name, or use a selection in the PCB editor.

Route only the 3V3 connection from the regulator to the sensor.

Route the connections for the selected parts. Keep the existing traces.

Select traces, vias, or parts in the PCB editor. Open Chat and describe the work you want on the selection. Flux sees the selected objects.

Set power trace widths

Ask Flux to route power rails, switch nodes, and ground with widths from the current requirements or width rules. Flux can connect power and ground pads to copper planes with vias.

Route the 5 V power path for 2 A using the board's width rules. Connect the GND pads to the ground plane with vias.

Open Chat and name the net and its current or trace width. For more prompts and trace-width rules, see Set power trace widths.

Choose routing layers

Tell Flux which layers to use for power, signals, and high-speed routes.

Use the top layer for the USB differential pair and the bottom layer for the remaining signals.

Keep the ground plane on layer 2. Route the 3V3 power path on layer 3.

Open Chat and name the layers for each net or group. See Stackup Editor to set the board's layers and layer properties.

Route a flex or rigid-flex board

Ask Flux to route your flex or rigid-flex board with the layer and via rules of each area.

Route the board. Keep the flex arm on L1 and L2 and put no vias in the flex areas.

Open Chat and name the layers and areas for the routes. See Flex and Rigid-Flex Boards.

Route differential pairs

Ask Flux to route a differential pair with the pair width, gap, and skew requirements.

Route USB D+ and D- as a 90 ohm differential pair. Keep the pair together from the connector to the MCU.

Route the two sensor interface nets as a differential pair on the top layer.

Set the pair properties and target impedance before routing. See Impedance control for pair setup and Positioning and routing for the editor workflow.

Route high-speed interfaces and match lengths

Ask Flux to route high-speed nets, tune their lengths, and match them within a tolerance.

Route the USB differential pair at 90 ohms from the board stackup. Tune the pair to a 0.15 mm length mismatch and keep it on layer 1.

Length-match the DDR data lanes to the strobe within 0.25 mm. Use the controlled impedance targets from the stackup.

Open the Chat panel and name the interface, target impedance, and length tolerance. Review the layer and impedance rules in the Stackup Editor. Flux routes the pairs and tunes their lengths to the requested tolerance. For analysis of routed signals, see Signal integrity.

You can ask Flux to route clocks and interfaces such as USB, DDR, HDMI, LVDS, and PCIe. For buses and parallel groups, specify lane order and pitch.

Route the clock on the top layer. Route the parallel data bus with the specified lane order and pitch, and match its lengths within 0.25 mm.

Tune lengths and skew

Ask Flux to tune a net to an absolute length or match its pin-to-pin length to another net. Set a tolerance in millimeters and a maximum skew for a differential pair or group. Flux reports lane lengths and skew in the result. Trombone meanders are the default. You can also ask for accordion or sawtooth meanders.

Set DDR_DQ0 to 42 mm, within 0.2 mm. Match DDR_DQ1 to the pin-to-pin length of DDR_DQ0 within 0.2 mm.

Route the DDR data byte lanes as a length-matched bus to the strobe. Use this lane order and pitch, and keep the bus skew below 0.25 mm.

Route the PCIe TX and RX lanes as 85 Ω differential pairs from the stackup. Keep each pair's skew below 0.1 mm.

Route the QSPI signals as a bus in this lane order and match their lengths within 0.3 mm.

Route the SDIO data lanes as a bus with this lane order and pitch. Match them to the clock within 0.4 mm.

Plan DDR topology and timing budgets

Ask Flux to plan the topology of a DDR interface before it routes. Flux selects fly-by or T-branch routing for the address, command, and clock nets, and adds the termination. Flux calculates a timing budget from the trace lengths and the propagation delay of the stackup. Flux then sets the length and skew targets from that budget and routes to them.

Plan a fly-by topology for the DDR4 address, command, and clock nets to the two memory chips, with VTT termination at the end. Then route it.

Calculate the timing budget for the DDR3 interface at 800 MHz from the stackup. Set the length and skew targets for each byte lane from it.

Compare fly-by and T-branch topology for the LPDDR4 address bus on this board, and route the better one.

Report the propagation delay of each DDR data lane and its skew to the strobe in picoseconds.

Route RF and antenna feed lines

Ask Flux to route an RF or antenna feed line with its stackup requirements.

Route the antenna feed at 50 ohms using the width from the stackup. Keep it on one layer over a ground reference, with no vias and curved bends.

Open Chat and name the feed net, reference layer, and routing requirements.

Fan out dense parts

Ask Flux to fan out a BGA or route connections from fine-pitch ICs, QFNs, and dense connectors.

Fan out the BGA with vias using the board's clearance and via rules.

Route the BGA escape connections with blind and buried vias from the stackup.

Route the QFN and fine-pitch connector connections. Use neckdowns at the pads where needed.

Repair the acid trap at this via with a short dogbone trace.

Flux fans out BGA pads, uses neckdowns where needed, and repairs via acid traps with short dogbone traces. For HDI routing, configure blind, buried, or microvias in the stackup. See Vias in PCB Design.

Open Chat and name the parts or select them in the PCB editor before you ask.

Break out a USB-C connector

Ask Flux to connect the USB-C pins to the board nets and route the required signals.

Break out the USB-C connector. Connect VBUS and GND to the power nets, then route D+ and D- as a 90 ohm differential pair.

Route the USB-C data pair from J1 to the MCU. Keep the connector's power and ground pins connected to their matching nets.

Open Chat and name the connector and pair requirements. For connector placement and board fit, see PCB placement.

Refine, edit, or remove routes

Ask Flux to change trace width, layer, geometry, or bend radius. You can also ask it to reroute connections or delete copper.

Widen the selected power traces to 0.5 mm.

Move the selected signal route to the bottom layer and round its corners with a 1 mm bend radius.

Reroute the SPI_CLK connection between U1 and U3. Replace its existing traces and vias and reconnect the pads.

Delete the traces of the TEST net without reconnecting it. Keep protected copper unchanged.

Select the relevant traces or vias in the PCB editor, then open Chat and describe the edit. For deletion, you can name a trace, a net, or an area. Flux skips protected copper when it deletes copper. Ask for a reroute to replace existing copper and reconnect the pads, or ask for deletion to remove copper without reconnecting.

Keep your existing copper and approve changes

Ask Flux to preserve your copper and placement when you request routing.

Route the open connections. Keep my copper, layout rules, and component positions. Ask me about any change you need.

Flux asks before it changes your copper, your layout rules, or moves your parts. You approve each change. A routing request stays routing only unless you ask for placement work.

For each change, Flux names what it wants to change, the old and new values, and a recommended default. This includes trace width, clearance, and via rules, the Via In Pad rule, the board size, cuts into protected copper fills, and copper you drew. Flux keeps the protection state of your copper unchanged and moves only the parts you approve.

Read the proposed change in Chat and reply with the changes you approve.

Review open connections

Ask Flux to list open connections and explain what blocks them.

List each open connection with its net, pin pair, and what blocks it. Propose a change and recommend a default.

Flux runs airwire and design rule checks (DRC) when it finishes routing. Its report lists each open connection with its net, pin pair, what blocks it, and a proposed change. Changes can include a rule or layer change, more signal layers, a part move, or a larger board.

Read the report in Chat and answer the question to choose the next change. Open the project drawer and select Review to see the design checks.

Last updated on

Was this page helpful?